It's not necessarily the case that each input gate is on a path to the output gate. Determining if there is a path in a directed (acyclic) graph from one node s to another node t is NLOGSPACE-complete, so it is not a condition that you can arbitrarily enforce on (say) LOGSPACE-uniform circuits. It is easy to enforce this condition without loss of generality on P-uniform circuits: if you only require that the circuit be constructed in polynomial time, then after building the circuit it is easy to compute the strongly connected components of the graph representing the circuit, and throw out all gates that do not have a path to the output gate. Hence the inputs that do not eventually connect to the output would simply not be present. (Note I am not sure if this is precisely what you want.)
Still, I can't think of any typical usages of circuits where some input gates may not have a path to the output. Most reductions involving circuits are from machines to circuits, and we typically assume that a machine reads all its input bits. And when one is trying to prove a circuit lower bound, one always considers functions that depend on every bit.
UPDATE: Here's a silly way to enforce the condition you want, but I don't know if it will help you in your particular case. Suppose for simplicity that the number of inputs $n$ is a power of $2$. Make a complete binary tree of $2n-1$ new gates (where all edges lead towards the root of the tree), so we have $n$ leaves. Label all nodes in the tree as $AND$ gates. For the $i$th leaf in the tree, lead in the inputs $x_i$ and $\neg x_i$. Now $OR$ the root of this binary tree with the output gate of your original circuit, and make this $OR$ your new output gate. Clearly every input now has a path to an output gate and the functionality of the circuit has not changed. Moreover this transformation is extremely uniform; I am pretty sure it can be made DLOGTIME-uniform. But is this really what you need for your problem?
